Semiconductor devices used in power electronics (hereinafter referred to as “power semiconductor devices” in some cases) especially for semiconductor devices having breakdown voltage of greater than or equal to 100 volts include diodes, metal-oxide-semiconductor field effect transistors (MOSFETs), and insulated gate bipolar transistors (IGBTs). The semiconductor devices are provided with termination structures for maintaining high breakdown voltage.
For example, such termination structure is provided in a semiconductor device (hereinafter referred to as a “vertical device” in some cases) in which current flows perpendicularly to a surface on one side in a thickness direction of a semiconductor substrate (hereinafter referred to as a “substrate surface” in some cases) so as to surround a region that functions as an active element (hereinafter referred to as an “active region” in some cases).
The termination structure have the function of maintaining high voltage generated in the substrate surface between the active region and an end portion of the semiconductor device. The high breakdown voltage of the semiconductor device cannot be achieved without the termination structure.
The breakdown voltage of the semiconductor device includes a reverse breakdown voltage of a diode and an off-state breakdown voltage of a transistor. In either case, the breakdown voltage is defined as a voltage capable of interrupting current, namely, the voltage being an upper limit voltage that passes no current.
In a state where the semiconductor device interrupts the current, a depletion layer expands inside the semiconductor substrate. The depletion layer can maintain the high voltage. The voltage exceeding the breakdown voltage is applied, causing an avalanche breakdown in an electric field concentrated portion inside the semiconductor substrate. This breaks the depletion layer, passing a short-circuit current.
For example, in a case where a PN junction diode (hereinafter referred to as a “PIN diode” in some cases) is formed of a low-concentration N-type semiconductor substrate and a high-concentration P-type implantation layer, the depletion layer mostly expands in the low-concentration N-type semiconductor substrate in an off state. The depletion layer maintains the high voltage. The breakdown voltage is limited by an end portion of the high-concentration P-type implantation layer, and specifically, an electric field concentration at an outer edge portion thereof.
A low-concentration P-type implantation layer is then formed adjacent to the end portion of the high-concentration P-type implantation layer, and the depletion layer thus expands both in the low-concentration N-type semiconductor substrate and the low-concentration P-type implantation layer. This relieves the electric field at the end portion of the high-concentration P-type implantation layer to increase the breakdown voltage.
The low-concentration P-type implantation layer is referred to as a reduced surface field (RESURF) layer or a junction termination extension (JTE) layer. Moreover, the termination structure is referred to as a RESURF structure.
The depletion layer also expands in the RESURF layer in the RESURF structure. To obtain the high breakdown voltage, the RESURF layer is preferably depleted almost completely to the outermost surface with a desired voltage. The conditions are specified by an implantation amount in the RESURF layer, such as a dosage amount or an implantation surface density.
In a case where the implantation amount in the entire RESURF layer is single, an optimal implantation amount is determined by a semiconductor material forming the semiconductor substrate without having a dependence on an impurity concentration of the semiconductor substrate. For example, the optimal implantation amount of silicon (Si) is approximately 1×1012 cm−2. The optimal implantation amount of silicon carbide (SiC) of polytype 4H is approximately 1×1013 cm−2. These values of the optimal implantation amounts are values in a case where an activation ratio of the impurities implanted is 100%. The values of the optimal implantation amounts are referred to as RESURF conditions.
The RESURF structure has problems below. To obtain the high breakdown voltage, an electric field is concentrated also at an outer edge portion of the RESURF layer in the RESURF structure. As a result, the high breakdown voltage is limited by the avalanche breakdown at the outer edge portion of the RESURF layer. In other words, the RESURF structure has limits on the high breakdown voltage.
The problem can be avoided by, for example, gradually decreasing the implantation amount in the RESURF layer toward the outside of the semiconductor substrate (for example, see Non Patent Document 1 and Patent Document 1). Such structure in which the implantation amount in the RESURF layer gradually decreases disperses the electric field concentrated points to a countless number of places and greatly reduces a maximum electric field inside the semiconductor. The structure of the RESURF layer is referred to as a variation of lateral doping (VLD) structure.
Moreover, the RESURF structure has the implantation amount in the RESURF layer gradually reduced toward the outside of the semiconductor substrate (for example, see Patent Document 2 and Patent Document 3). Effects similar to those in the case with the RESURF layer in the VLD structure disclosed in Non Patent Document 1 or Patent Document 1 can be obtained in the RESURF structure.
Specifically, in the case of the RESURF structure disclosed in Patent Document 2 or Patent Document 3, the electric fields are concentrated at the outer edge portion of the high-concentration P-type implantation layer, the boundary portion of the RESURF layers having different implantation amounts, and the outermost edge portion of the RESURF layer. Therefore, the effects of relieving the electric fields in the RESURF structure disclosed in Patent Document 2 or Patent Document 3 are inferior to the effects in the case where the RESURF layer in the VLD structure disclosed in Non Patent Document 1 or Patent Document 1 is used. However, as compared to the entire RESURF layer in which the implantation amount is single, the RESURF structure disclosed in Patent Document 2 or Patent Document 3 disperses the electric field concentrated points, thereby reducing the maximum electric field inside the semiconductor substrate.